The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, a method of manufacture therefor, and an integrated circuit including the semiconductor device.
Integrated circuits are well known and are extensively used in various present day technological devices and systems, such as sophisticated telecommunications and computer systems of all types. As the use of integrated circuits continues to grow, the demand for more inexpensive and improved integrated circuits also continues to rise. Thus, presently, an emphasis in the integrated circuit industry is to provide densely packed, faster devices at a competitive price.
Deep trench-isolation structures are currently being used to provide the requisite thermal and electrical isolation between the densely packed devices. More specifically, deep trench-isolation structures have found increased use in complementary bipolar processes using both vertical npn and vertical pnp bipolar transistors.
In one of those devices, for example the pnp bipolar device, the deep isolation trenches are vertically formed through various doped regions, specifically a p-type buried collector region, a lightly n-doped isolation tub, and a p-type substrate. After formation of the isolation trench, a dielectric material may be formed on the sidewalls and bottom surface of the isolation trench. The isolation trench could then be filled with an easy to deposit filler material, such as polysilicon.
A problem arises, however, with the above-mentioned device. Because the above-mentioned isolation structure includes a sidewall dielectric layer covered by polysilicon, an undesirable parasitic metal oxide semiconductor (MOS) device is formed. In one instance, the p-type buried collector and the p-type substrate would act as the source and drain, the n-doped isolation tub would act as the body of the MOS device, the polysilicon fill of the isolation trench would act as the gate and the trench sidewall dielectric layer would act as the gate oxide. If not properly engineered, the parasitic MOS device could detrimentally be turned on, or alternatively, cause a significant sub-threshold current from the buried collector to the substrate to arise.
The most notable approach for substantially preventing the parasitic MOS device includes replacing the polysilicon fill with a deposited/grown oxide. Although fixed oxide charges in the oxide fill can still affect the nearby silicon, the absence of a gate metal/polysilicon on a sidewall means the parasitic MOS device is substantially reduced.
A key disadvantage of using an oxide in place of the polysilicon, is the inability to completely fill the trench with the oxide. When a typical oxide deposition process is used, the oxide grows faster at the top of the trench and fills in with a gap deeper down in the trench. This gap, and inclusion of moisture and/or contaminants, may affect long-term reliability of the device.
In an alternative approach, one could dope the N-type isolation tub (isotub) with a heavier concentration of dopants. However, this approach lowers the breakdown voltage of the device, as well as increases the overall capacitance of the device. Unfortunately, lower breakdown voltages and increased capacitance lead to degradation in device performance.
Accordingly, what is needed in the art is a semiconductor device and a method of manufacture therefor that does not experience the problems experienced by the prior art semiconductor devices.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer. It is believed that the interconnect beneficially turns off a parasitic MOS device in the semiconductor device.
The foregoing has outlined, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.